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HD74BC640A
Octal Bus Transceivers With 3 State Outputs
REJ03D0290-0200Z (Previous ADE-205-026 (Z)) Rev.2.00 Jul.16.2004
Description
The HD74BC640A provides high drivability and operation equal to or better than high speed bipolar standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5 of high speed bipolar logic IC. When the frequency is 10 MHz. The device has eight bus transceivers with three state outputs in a 20 pin package. Each device has an active low enable input (G) and a direction control input, DiR. When DiR is high, data flows from the A inputs to the B outputs. When DiR is high, data flows from the B inputs to the A outputs. When enable inputs (G) is high, disables both A and B ports by placing then in a high impedance.
Features
* Input/Output are at high impedance state when power supply is off. * Input pins can be open, when not used, owing to built in input pull up circuit. * Input is TTL level. * Wide operating temperature range Ta = -40 to +85C. * Ordering Information
Part Name HD74BC640AFPEL Package Type Package Code FP Package Abbreviation Taping Abbreviation (Quantity) EL (2,000 pcs/reel)
SOP-20 pin (JEITA) FP-20DAV
Function Table
Control Inputs G L L H H: L: X: High level Low level Immaterial L H X DIR B data to A bus A data to B bus Isolation Operation
Rev.2.00, Jul.16.2004, page 1 of 7
HD74BC640A
Pin Arrangement
DiR A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC G B1 B2 B3 B4 B5 B6 B7 B8
(Top view)
Absolute Maximum Ratings
Item Supply voltage Input diode current Input voltage Output voltage VCC IIK VIN VOUT Symbol Rating -0.5 to +7.0 30 -0.5 to +7.5 -0.5 to +7.5 V mA V V Unit
Off state output voltage VOUT(off) -0.5 to +5.5 V Storage temperature Tstg -65 to +150 C Note: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input voltage Ouput voltage Operating temperature VCC VIN VOUT Topr Symbol 4.5 0 0 -40 Min 5.0 -- -- -- Typ 5.5 VCC VCC 85 8 Max V V V C ns/V Unit
Input rise/fall time*1 tr, tf 0 -- Note: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Rev.2.00, Jul.16.2004, page 2 of 7
HD74BC640A
Logic Diagram
DiR G B1 B2 B3 B4 B5 B6 B7 B8
A1 A2 A3 A4 A5 A6 A7 A8
Electrical Characteristics (Ta = -40 to +85C)
Item Input voltage Output voltage Symbol VIH VIL VOH VOL Input diode voltage Input current VIK II 4.5 4.5 4.5 4.5 4.5 5.5 5.5 5.5 5.5 Output short circuit current*1 Off state output current Supply current IOS IOZH IOZL ICCL ICCH ICCZ 5.5 5.5 5.5 5.5 5.5 5.5 VCC (V) Min 2.0 -- 2.4 2.0 -- -- -- -- -- -- -- -100 -- -- -- -- -- Max -- 0.8 -- -- 0.5 0.55 -1.2 -250 100 1.0 100 -225 -100 -250 29.5 2.5 4.5 Unit V V V V V V V A A A A mA A A mA mA mA IOH = -3 mA IOH = -15 mA IOL = 48 mA IOL = 64 mA IIN = -18 mA VIN = 0 V An or Bn, VIN = 5.5 V DiR or G, VIN = 5.5 V DiR or G, VIN = 7 V VO = 0 V, VIN = 0 or 5.5 V VO = 2.7 V VO = 0.5 V VIN = 0 or 5.5 V All outputs is "L" VIN = 0 or 5.5 V All outputs is "H" VIN = 0 or 5.5 V All outputs is "Z" Test Conditions
ICCT*2 5.5 -- 1.5 mA VIN = 3.4 or 0.5 V Notes: 1. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. 2. When input by the TTL level, it shows ICC increase at per one input pin.
Rev.2.00, Jul.16.2004, page 3 of 7
HD74BC640A
Switching Characteristics (CL = 50 pF)
Ta = 25C VCC = 5.0 V Item Propagation delay time Symbol Min tPLH 3.0 tPHL tPLH Output enable time tPHL tZH tZL tZH Output disable time tZL tHZ tLZ tHZ Input capacitance Output capacitance tLZ CIN CI/O 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 Max 6.0 6.0 6.0 6.0 9.0 9.0 9.0 9.0 8.0 8.0 8.0 Ta = -40 to +85C VCC = 5.0 V 10% Min 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 -- -- Max 7.0 7.0 7.0 7.0 11.0 11.0 11.0 11.0 10.0 10.0 10.0 10.0 pF pF VIN = VCC or GND VI/O = VCC or GND Unit Test Conditions ns An to Bn ns ns ns ns ns Bn to An G to Bn G to An G to Bn G to An
3.0 8.0 3.0 (Typ) 15.0 (Typ)
Rev.2.00, Jul.16.2004, page 4 of 7
HD74BC640A Test Circuit
VCC G Input
See Function Table
VCC
Output A1 S1 500 B1 CL = 50 pF 450 50 Scope OPEN 7V
*4
Pulse Generator Zout = 50
DIR
Notes:
1. 2. 3. 4.
CL includes probe and jig capacitance. A2-B2 to A8-B8 are identical to above load circuit. S1: Input-Output change switch. Open: tPLH, tPHL, tZH tHZ 7 V: tZL, tLZ
Waveforms-1
tf Input 90 % 1.5 V 10 % tr 90 % 1.5 V 10 % t PHL 1.5 V 1.5 V VOL 3V 0V VOH Output
t PLH
Rev.2.00, Jul.16.2004, page 5 of 7
HD74BC640A Waveforms-2
tf G 90 % 1.5 V 10 % t ZL Waveform - A 1.5 V t ZH Waveform - B 1.5 V t HZ VOH - 0.3 V tr 90 % 1.5 V 10 % t LZ VOL + 0.3 V 3V 0V 3.5 V VOL VOH 0V
Notes:
1. tr = 2.5 ns, tf = 2.5 ns 2. Input waveforms: PRR = 1 MHz, duty cycle 50% 3. Waveform-A shows input conditions such that the output is "L" level when enable by the output control. 4. Waveform-B shows input conditions such that the output is "H" level when enable by the output control.
Rev.2.00, Jul.16.2004, page 6 of 7
HD74BC640A
Package Dimensions
As of January, 2003
12.6 13 Max
20
Unit: mm
11
1
10
5.5
0.80 Max
2.20 Max
*0.20 0.05
0.20 7.80 + 0.30 -
1.15
1.27
*0.40 0.06
0.10 0.10
0 - 8
0.70 0.20
0.15
0.12 M
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
FP-20DAV -- Conforms 0.31 g
Rev.2.00, Jul.16.2004, page 7 of 7
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